Semiconductor devices such as silicon devices having exposed p-n junctions, are generally passivated by depositing an inert material such as silicon dioxide or silicon nitride thereover. The use of oxygen-doped polycrystalline silicon as a passivating layer is described in U.S. Pat. No. 4,014,037. This material provides a number of good passivating properties, but is sensitive to ionic motion which eventually may result in degraded electrical characteristics in the device. Therefore, it has been proposed to deposit a layer of silicon nitride on top of an oxygen-doped silicon layer to inhibit ion migration.
Regardless of the passivating materials used to protect the surfaces of semiconductor devices, and the above mentioned materials are only examples, another problem arises when these layers are defined for the purpose of opening holes to expose the surface of the semiconductor body where electrical contacts are to be made.
Openings in the layers of passivating material are usually defined using various combinations of masking materials, photoresists and etching solutions. For example, in the past it has been common practice to cover the top silicon nitride passivating layer (or layer of other passivating material) with a layer of a masking material such as silicon dioxide or borosilicate glass and then define this layer and the passivating layers beneath with the aid of an organic photoresist.
It is well known that photoresist layers are subject to imperfections such as pinholes, especially in devices having irregular contours like mesa transistors. When the pinholes extend completely through the photoresist layer, etchant solutions subsequently used to remove underlying masking material where contact openings are being made, will also remove masking material beneath the pinholes and, subsequently, these pinholes may be propagated through the passivating layers to the device surface. The problem is aggravated because pinholes also often occur in the masking layer and in the passivating layer.
The underlying reason why material beneath the pinholes in the photoresist layer is etched completely through the masking and passivating layers at the same time as the much larger contact openings are etched through these same materials is that etching occurs at about the same rate, regardless of the diameter of the hole being etched. That is, these etchants have been "surface rate" controlled.